1. Technical Field of the Invention
This invention relates to electronic circuit design. More specifically, it relates to placement of voltage and ground contacts in a decoupling capacitor for application specific integrated circuit (ASIC) libraries.
2. Background Art
Current CMOS technology integrated circuits (ICs) contain millions of logic gates switching at very high speeds. Decoupling capacitors are required across the power supply busses VDD and GND to reduce the switching noise which can affect the timing of the individual gates on the chip. As CMOS technologies have progressed, higher circuit speeds are realized and increased wire resistance results from smaller metal cross sections in the power bussing. Adding larger areas of decoupling capacitors to an IC requires large areas of polysilicon which increase the probability that a single processing defect could cause a short from VDD to Ground in the capacitor area. This would render the entire chip useless and reduce the wafer yield thereby increasing the cost of the functional chips.
Heretofore a first solution has been to add a gating device in series to the decoupling capacitor for two reasons: first, to turn off the leakage path from VDD to Ground for testing purposes; and, second, to gate off the defective device to save the chip should a defect cause a power supply short in the capacitor area.
There are a few drawbacks to the above solution that make implementation difficult, and the usefulness of this approach is bandwidth limited for high speed applications. The gating device is usually an NFET (NFET are typically smaller than PFET for the same lgs current). This NFET is sized such that there is a low impedance from gate-to-source. The low impedance in series with the capacitor is required to reduce the RC which limits the bandwidth of the network. This low impedance NFET must be very large physically which may take up as much area as the capacitor itself. The large NFET must also have a large gate area which increases the gate capacitance, which in turn forces the chip designer to use a large driver to drive the gate. Another draw back is the fact that the decoupling capacitor has an input pin. Ideally a decoupling capacitor is a passive device without any wireable pins. When thousands of decoupling capacitors are required on a chip, thousands of gates must be wired and driven by circuit buffers from one or more primary input pins. The wiring and buffering is further complicated when it is desirable to isolate and degate the defective capacitor. A substantial amount of circuit area and wireability is lost when implementing such schemes.
A second solution has involved the addition of an integrated circuit resistor, resulting in a capacitor with a large RC. This solution also results in a relatively large area requirement for the resistor.
It is understood that coupled noise and leakage are driving down circuit yields. This is cause by highly resistive and closely spaced circuit wiring (coupled noise) and extremely thin gate oxides causing current leakage. A large RC means that the capacitor can not function as a decoupling capacitor, or has limited affect as a decoupling capacitor. On the other hand, a low series resistance capacitor allows more leakage current. Consequently, there is a need in the art for a decoupling capacitor the limits leakage current by design without adding a resistor in series.
Such decoupling capacitors as gated capacitors, capacitors with series resistance of a chosen resistance, and a series of capacitors pfet/nfet decoupler with NFET drain tied to PFET gate and Pfet drain tied to NFET gate which have previously done well at high-frequency decoupling have not performed successfully in newer technologies due to their large series resistance Referring to FIGS. 1 and 2, the first solution described above uses a gating transistor TN2 102 that can be turned on or off by switching the input GATE 104 high or low. When turned off, such as during test, gate 102 is open. The leakage current through the capacitor CAP1 106 from VDD 110 to GND 108 is limited by the size of gating transistor TN2 102 when TN2 is on. This approach requires a very large device TN2 102, a buffer TN1 112 and TP1 114 and an input pin 100 for gate 104, all added to the layout of capacitor CAP1 106.
Referring to FIG. 3, the second solution described above uses an integrated circuit resistor R1 116 added in series to capacitor CAP1 106. Referring to FIG. 4, this solution requires the area overhead of the integrated circuit resistor 116, which reduces the layout density of decoupling capacitor CAP1 106 considerably.